11/24/2023 0 Comments Width of transistor gate![]() ![]() the traversal of the gate material(s) over the vertical fin topography, with minimal line edge roughness and variabilityĭue to the increase in the effective width of the gate traversal over the fin – the sides and the top – the FinFET drive current per unit area is increased over an equivalent planar device.the etching of the silicon fin, with uniformity in sidewall slope and fin thickness.The key process development steps for the FinFET were: The FinFET gate input traverses over the sides and top of the fin, offering better electrostatic control of the fin channel, and thus, reduced “off” leakage current. The FinFET introduced a vertically-oriented channel, with lateral current flow between drain and source nodes when the device is “on”. The scaling of planar FETs results in increasing subthreshold leakage current.Īs the continued scaling of planar FETs faced the leakage current obstacle, two new transistor topologies were proposed – the vertical SGT and the lateral FinFET, shown below. The increase in static leakage power was problematic for the emerging mobile and consumer applications seeking long battery life.įigure 2. However, reductions in the device length led to an increase in the subthreshold channel leakage current, when the (n-type or p-type) FET transistor gate input was in the “off” non-conducting state. The results of these PPA advances in successive fabrication processes provided both faster performance and greater circuit density, even with scaled supply voltages. The scaling of (minimum) lithography dimensions for these devices offered significant benefits in performance, power, and area. Planar field-effect transistors had been the workhorse technology throughout decades of integrated circuit fabrication.
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